1. Field
The invention relates to chucks for supporting substrates during processing, such as electrostatic chucks for semiconductor substrates. The invention is particularly beneficial for fabrication of solar cells, which is done using relatively thin silicon wafers.
2. Related Arts
Electrostatic chucks (ESC) are well known in the semiconductor industry. Most chucks have flat and smooth top surface, i.e., the surface contacted by the wafer. Conversely, some chucks have mesas on the top surface. See, e.g., U.S. Pat. No. 5,903,428 disclosing mesas formed from a thin film deposition of a highly-resistive dielectric. The thin-highly resistive film prevents excess DC standby current as well as reduces the dependence of the electrostatic chuck performance on the wafer backside morphology and composition. Another example is U.S. Pat. No. 7,869,184 disclosing a method of modifying the capacitance profile of an electrostatic chuck by adjustment or initial fabrication of the height of a mesa configuration of an insulating layer of the chuck. FIGS. 1 and 2 illustrate prior art chucks having mesas. In the prior art the mesas 106 are generally round “islands” that are used to hold the wafer 108 at a predetermined height 114 from the top surface 110 of the chuck 100. Electrode 104 applies attractive force under the mesas 106. In such configuration the back surface of the wafer only contacts the mesas and not the top surface of the chuck. One of the main reasons to hold the wafer at a distance from the top surface of the chuck is to reduce the chucking power, so that it is easier to remove the wafer after processing. Thus, the height of the mesas and the chucking power are designed to keep the wafer on top of the mesas, away from the top surface of the chuck.
During some process steps the wafer's temperature may increase. This happens, e.g., during plasma processing or during ion implant. Most process steps are performed over the entire surface of the wafer, so that the wafer's thermal expansion does not affect the processing. However, some processes are performed such that only parts of the wafer's surface are exposed to processing. For example, when performing ion implant using a so-called shadow mask, only the ions passing through the openings in the mask reach the wafer, such that the resulting implant is patterned according to the openings in the shadow mask. Thermal expansion of the wafer may not pose a problem, unless the mask openings must be aligned to certain areas of the wafer with high precision. In such a case, thermal expansion may pose a problem, as the mask may be aligned to the wafer at one temperature, but then due to thermal expansion of the wafer that alignment may be frustrated. Accordingly, there is a need in the art to ensure that thermal expansion of the wafer during processing would not cause misalignment of the wafer during processing.